WEBINAR: Thermal Management Guidelines for GaN Transistors
With Dr. Roy Hou, Staff Applications Engineer at GaN Systems
GaN Systems is back with another of their highly successful webinars, this time it’s all about thermal management.
In This Webinar You’ll Learn:
- The performance impact of thermal management
- What the most important measurements and calculations are
- How to maximize performance with GaN Systems top-cooled and bottom-cooled transistors
Please explain availability of IMS material and optional sizes and fabrication options.
We provide two IMS designs with different sizes. Please refer to slide #20. You can also find the IMS user manual >
Is there any good and reliable method of measuring the die temperature, when using the thermal camera I would think one does read a slightly lower value because of additional obstructive layer on top of the device. Is there knowledge about how close that measurement is to the real junction temperature?
The GaNPX package is quite thin. Hence, we can measure the temperature on the very top of the bottom-cool device (or the very bottom of the top-cool device) and this package temperature is a good approximation for device junction temperature. The difference is within 1 degree C between the measurement temperature and the junction temperature.
Have your GaN transistors have been applied to any systems with a power requirement of less than 25kW?
Yes. With high current capability and ease of parrallelling devices, our devices have been applied in systems greater than 25kW.
Can you compare IMS to top-side cooled - advantages and disadvantages of each?
In general, IMS achieves better thermal performance than top-side cooled, primarily because a TIM is not used with the IMS. However, the trade-off really depends on your converter system structure and its layout. Some users prefer top-cooled device, as its heat transfer path and electrical current path are also not overlapped. Refer to the IMS user guide >
Do you have any recommendations for calculating switching times? This tends to be the most challenging part of accurately calculating the power losses. If this is not correct, it also makes it harder to properly gauge the benefits of GaN technology.
To achieve best accuracy, we highly recommend to do double pulse test and measure the actual Eon and Eoff. A proper de-skew is critical on switching loss measurement.
Do you have any comparison for top cooling with thermal pad and bottom cooling with IMS? Under same loss
Slide #25 and 27 show the thermal resistance comparison among different thermal designs, including top-cooling with thermal pad and bottom-cooling with IMS.
In order to estimate turn-on and turn-off loss of GaN, is the drain current variation or channel current variation an essential parameter? If the channel current is more important parameter, can it be estimated from SPICE package program?Toggle Title
Yes, Eon/Eoff are dependent on drain current. Eon/Eoff can be estimated by SPICE models. Refer to our app note GN008 for details >
Is it the traction inverter of 10 kW cost compatible with SiC or Si for 48 applications?
Yes. Our customers have developed up to 25kW inverters and have shown 3x power density improvement and up to 10% system cost savings.
Could you please suggest some methods of measuring the device temperature for high frequency applications?
You can use a thermal camera to measure the device temperature.
Can you compare thermal transient behavior top-side cooling vs.bottom-side cooling? Thank you!
The detailed 4 stage junction-to-case thermal model is available in our datasheets.
Will dV/dT switching couple with the heat sink so that it will cause EMI issues?
The heat sink is not connected with the switch device. A TIM is placed between the heat sink and switch for electrical isolation. For increased EMI performance, you can the floating heat sink to earth.
Do you have a detailed CAD model of the GaN that can be used for FEA thermal simulations?
Do you have a detailed CAD model of the GaN that can be used for FEA thermal simulations?
For IMS designs, the thickness of the Dielectric Layer is so small (30-200um), parasitic capacitance will be several times larger then conventional solutions, any idea about this concern?
Yes, the parasitic capacitance between the switching node and base plate is ~100pF, depending on the polygon area. The effect on switching performance is negligible. The effect on EMC also depends on the grounding of the base plate, but generally speaking, the EMI is similar to PCB based design.
What is the recommendation for ZVS application of GaN with only turn off loss, what needs to be taken care of, I was using 25mohm device ?
For turn-off loss Eoff, it shall be only the VI overlapping loss. The capacitive Eoss loss actually is part of the Eon loss. GaN obtains low turn-off loss and gate driver loss. As you go to higher switching frequency, the losses that require attention are mainly the Eoff loss and gate driver loss.
Toggle TitleFor the bottom-cooled device with IMS solution, there’s limited space for component placement and a driver board is needed. Could you please comment on the parasitic gate loop inductance introduced by this modular design? What is the favorable switching frequency when taking this gate loop inductance into account?
Magnetic flux cancellation design is applied between the IMS board and the bottom layer of the driver board. The distance between the two boards determines the cancellation effect. The gate loop inductance is ~6 nH in this design, with a 4.5mm distance between the two boards. It is slightly higher than the single PCB design (~4nH), but is still good for ~MHz applications. For more information, refer to this link >
For IMS cooling applications, would you recommend a metal core in the middle, or a metal base on the bottom side?
IMS material can be attached to the heatsink directly. Refer to this link for more information about IMS-based design >
For the IMS heatsink, is it floating or grounded?
On the IMS evaluation board, we have its heatsink floating. To achieve better EMI performance, you might want to connect the heatsink to earth.
Do you have a design with GaN Systems devices for a grid-tie inverter? If yes, How about the thermal issues in this case?
This is an application suitable for GaN. However, we do not have a publicly available grid-tie inverter reference design. We have published a technical paper regarding the IMS-based T-type inverter. Please refer to the paper with the link >
Is there a reason why GaN Systems top cooled devices do not have a kelvin source?
This is because for top-cool device, the GaN layer is already on the very bottom (near the PCB). Therefore, the Kelvin source on the package is not necessary. For external layouts, you may still want to layout a pseudo-Kelvin source to separate the driving loop and power loop.
What percentage of power loss normally exists for a GaN device?
This depends on your switching frequency, load current, and thermal conditions, etc. Generally speaking, for GaN-based hard-switching half-bridge, you can expect it introduces power loss in the range between 0.2% to 0.7%
I am using the SPICE models for a while now - are there any updates on these models recently?
Yes. We now offer 2 levels of SPICE model: Level 1 and Level 3. Level 1 is a simplified version and Level 3 offers detailed thermal model and parasitic inductances. The models are available in the product section of our website
How can you calculate the junction-to-heatsink thermal resistance?
We measure the heatsink temperature and then we can calculate the junction-to-heatsink Rth.
Is the Tj in your test the maximum temperature in the chip or the average temperature in the device?
It is the maximum temperature in the chip.
On page 26 or in general, how did you define the temperature (ambient) for the RTH_JA or where did you measure this temperature?
We use a thermocouple to measure the temperature near the device for the ambient temperature measurement
Do you plan to expand the family of 48V products with a higher power density than GS61008P? Any top cooled solution for 48V at + 150 A ?
Higher power (higher current) devices for 48V applications is part of our roadmap. Look for more information on this product in the short term.
How do switching losses vary with temperature?
Eon and Eoff are both low. Eon increases with increased temperature. Eoff does not change with temperature.
Where do you see limitations in paralleling your devices?
There are designs with up to 8 devices in parallel without issue. Limitation is not of concern. Designers do need to use good layout technique. Refer to our parraleling appnote >
Top cooling and bottom cooling, which one is better?
They are quite similar. It really depends on how you want to cool the device, your system structure, and converter circuit layout.
What thermal modeling software do you use?
We use FloTHERM for all the simulations in this webinar
Do you specify soft-switching Coss losses?
The capacitive Eoss loss is listed on the datasheet and it occurs in hard-switching on. If the application is ZVS soft-switching, this loss is not in the system.
Which FEA software do you use for the thermal analysis?
We use FloTHERM for all of the simulations in this webinar
Does the drain current contribute anything to the top side temperature reading?
No, the drain current does not impact the top side temperature reading.
What is the thermal time constant of the top side measurement? What is the duration of the measurement?
It depends on the thermal capacitance value. From junction to case, it can be several micro seconds. To heatsink or ambient, it depends on the specific PCB, heatsink design, etc.
Is IMS only limited to GaN devices? Or is it also possible to design packages with Si and SiC devices as well?
It is possible for all SMD power switches.
What is that pressure in kPa?
50 PSI is ~344 kPa, 100 PSI is ~689 kPa
Do your transistors come with integrated thermistors for safety monitoring?
Although not available today, this is a feature in our roadmap
On Slide 19, where are the capped Vias?
The capped vias are under the thermal pad of the device
Speaker: Ruoyu (Roy) Hou
Power Electronics Application Engineer, GaN Systems Inc.
Dr. Ruoyu (Roy) Hou is a Power Electronics Application Engineer at GaN Systems Inc. He received his M.S. degree from the Illinois Institute of Technology, Chicago, IL, USA and his Ph.D. degree from the McMaster University, Hamilton, ON, Canada, both in electrical engineering.
Formerly an electrical engineer with GE Transportation, Dr. Hou was a post-doctoral research fellow at McMaster Automotive Resource Centre (MARC), a Canada-based Excellence Research Center. His interests include power electronics, modeling and loss analysis of wide-bandgap (WBG) semiconductor devices, and GaN-based high-power converter and its magnetic design.
Dr. Hou was a recipient of the ECCE Best Paper Award in 2016 and a co-recipient of the Chrysler Innovation Award for the Automotive Partnership Canada (APC) project in 2014.
Moderator: Paul Wiener
VP Strategic Marketing at GaN Systems
Paul Wiener is GaN Systems’ Vice President of Strategic Marketing. Prior to joining GaN Systems, Paul led the power magnetics business unit at Eaton. Paul brings more than 25 years’ experience in operations, sales and marketing, and business development. His experience includes vice president of sales at Fultec Semiconductor Inc. and several management roles at Genoa, BroadLogic, and Raychem.