Webinar: Optimum Power Stage Design with GaN for Next Generation Power Supplies
In this webinar:
- GaN power stage design for several topologies and power levels will be detailed
- Examples of thermal and electrical performance optimization will be reviewed
- You will learn how to implement proven power stage design techniques to maximize performance in applications ranging from consumer chargers and adapters, to enterprise and industrial power supplies, to automotive OBC and traction power modules.
Questions & Answers
Why there is a nonlinear rise for the turn off loss at Vgsoff=0V?
The relationship between switching-off loss and drain current is not linear. At higher current swithcing-off, the millar plateau voltage can be above Vth during the dv/dt switching period resulting in higher losses. Applying negative gate voltage will help reduce this effect resulting in lower switching-off losses.
In the flux cancellation method, it is required to use vias for the high current path to go from top layer to middle layer. Won’t the vias add additional parasitic series inductance which may cause more ringing in the "gate source return path"?
The use of vias is necessary to apply flux cancellation in the power loop to reduce the power loop inductance. Having a lateral power loop to avoid using vias will result in a much larger power loop compared to the application of flux cancellation with several vias as seen by the example PCB inductance values in the webinar. If a kelvin source connection is applied, we avoid common power loop inductance in the gate loop and will not cause more ringing in the gate source return path.
How will gate oscillation be handled in a GaN application with paralleled switches?
Following discussed layout steps with symmetrical gate loops and designing a robust gate circuit should mitigate noise for paralleled designs. Including distributed gate and source resistances for each device in your gate loop will also help reduce gate ringing. Please see our application note GN004 ‘Design considerations of paralleled GaN HEMT’ for more information.
How many devices can be paralleled reliably in theory?
We have customer experience paralleling 8 GaN devices reliably. It can be higher as long as good layout design is maintained. Please see our application note GN004 ‘Design considerations of paralleled GaN HEMT’ for more information.
How can we take advantage of high dv/dt while keeping the EMI filter size optimized?
The high dv/dt of GaN enables the reduction of switching loss and allows for the increase in system switching frequency. The increase in system switching frequency enables the reduction of input EMI passive component value and therefore size. Sometimes there is a tradeoff between achieving high dv/dt and to pass EMI standards by tuning the GaN switching speed.
How do you see the market for GaN in motor drive applications, given the limitations of dv/dt on the machine side?
There are several advantages using our 100V GaN devices for motor drive applications. Designs have been successful because dv/dt limitations for 48V applications can be up to 20V/ns which can be easily achieved by adjusting the external gate resistance without significant compromise of switching efficiency. The application of GaN will lead to lighter weight and smaller size drivers with smooth high frequency and high efficiency operation.
What are the benefits of a discrete transistor with external driver?
Many power designs implement a controller + integrated driver. The first advantage of a discrete transistor is the elimination of a “double-driver” scenario which complicates a design and makes it more expensive. Secondly, a discrete transistor design provides more driving flexibility and simplicity. You can control the slew rate for EMC, apply negative voltage to minimize switching off losses and parallelling is much easier. All benefits versus using integrated GaN.
Regarding the copper shields underneath the heatsink, whats the electrical connection to get a proper EMI shielding? Earth? Or one bridge supply voltage rail?
The copper shield should be connected to the ground or virtual ground considering the design.
Which CAD tools does your company use for simulation and layout?
We primarily use Ansys Maxwell Q3D
What isolation material do you use to insulate the source potential of GaN thermal pads from the copper shield?
There are several Thermal Interface Material (TIM) materials which can be used to isolate the GaN source thermal pad. The selection depends on required electrical isolation, thermal conductivity and cost.
Why does GaN Systems include a ferrite bead in gate loop? Isn’t adding more inductance not good for fast switching?
Typically, ferrite beads are not required in the gate loop layout, but they can help reduce high frequency ringing without sacrificing switching speed.
Moderator: Paul Wiener
VP Strategic Marketing at GaN Systems
Paul Wiener is GaN Systems’ Vice President of Strategic Marketing. Prior to joining GaN Systems, Paul led the power magnetics business unit at Eaton. Paul brings more than 25 years’ experience in operations, sales and marketing, and business development. His experience includes vice president of sales at Fultec Semiconductor Inc. and several management roles at Genoa, BroadLogic, and Raychem.