FAQ - E-mode HEMTs
What is the recommended gate drive voltage?
+ 6 V is recommended for the gate drive.
What is the absolute maximum gate to source voltage rating?
We specify 7.0 V as the absolute maximum DC voltage setting for the gate drive and also specify that for transient spikes, the gate can survive up to ± 10 V. These specifications allow designers to easily use 6.0 V or even 6.5 V gate drive settings.
Can I use a 5V for the gate drive?
A 6 V gate drive voltage is recommended for the maximum efficiency point, where the Enhancement mode HEMT (E-HEMT) is fully enhanced and reaches its optimal efficiency point. A 5 V gate drive can be used but may result in a lower operating efficiency.
Do I have to use a negative gate voltage for turning it off?
No. Inherently a GaN Systems E-HEMT does NOT require a negative gate bias to turn off. Negative gate bias ensures safe operation against the voltage spike on the gate, but at the same time, it increases the reverse conduction loss. For more details, please refer to the gate driver application note "GN001 How to Drive GaN Enhancement Mode Power Switching Transistors."
How can I control the device slew rate?
Similar to a silicon MOSFET, the external gate resistor can be used to control the switching speed and slew rate.
What is the recommended gate resistance to start with?
It is recommended to start with a turn-on gate resistor in the range between 20Ω to 47Ω, and then adjust the resistor to achieve the desired slew rate. Lower turn-off gate resistance is recommended for better immunity to cross conduction. Please see the gate driver application note (GN001) for more details.
What is the Source Sense (SS) pad and how do you use it?
The Source Sense pad is a Kelvin connection to the source. It is designed to be used by a gate drive circuit to exclude the common source inductance from the gate drive loop. To make proper use of the source sense connection, the gate drive power supply (either isolated or shared with the control circuit) ground return should be referenced to the SS pad using a star point connection. Unlike power devices that use wire bonds internally for connections, our GaNPX™ packaging utilizes no wire bonds. So, our source connection is already very low inductance. Utilizing the Source Sense pad can improve drive performance but may not be necessary in all systems.
The Top-side products don’t have a Source Sense pin. Why not?
Unlike power devices that use wire bonds internally for connections, our GaNPX™ packaging utilizes no wire bonds so our source connection is already very low inductance. We’ve learned that simply by using a “Source Sense” connection on the PCB to either side of our Source pad, the function can easily be implemented. Allowing customers to connect to either side of our Source pad accomplishes the function and allows layout flexibility. Utilizing the Source Sense pad can improve drive performance but may not be necessary in all systems.
Can I use a standard MOSFET gate driver?
Yes, a standard MOSET driver can be used as long as it supports 6 V for gate drive and its UVLO is suitable for 6 V operation. Gate drivers with low impedance and high peak current are recommended for fast switching speed.
Can I save money on my gate driver?
Yes, GaN Systems E-HEMTs have significantly lower QG when compared to equally sized (RDSON) MOSFETs, so high speed can be reached with smaller and lower cost gate drivers.
Can I use a standard half bridge MOSFET/IGBT driver for high side gate drive?
Many half bridge MOSFET drivers are not compatible with 6 V gate drive for GaN enhancement mode HEMT due to their high under-voltage lockout threshold. Also, a simple bootstrap method for high side gate drive will not be able to provide tight tolerance on the gate voltage. Therefore special care should be taken when you select and use the half bridge drivers. Alternatively, isolated drivers can be used for a high side device. Please see the gate driver application note GN001 for more details.
The Top-side products have two Gate pins. Why? Do they need to be connected on the PCB?
We’ve implemented two gate drive pins on our Top-side packages to ease the layout when paralleling devices. Both of these gate drive pins are internally connected to the gate, so only one needs to be connected, although connecting both may lead to minor timing improvements at very high frequencies. Two gates are not designed to be used as a signal conductor. When multiple devices are used in parallel, it is NOT recommended to use dual gates to pass down the gate drive signal to the next device. Always use a wide track or a polygon on PCB to distribute the gate drive signals to multiple devices and keep the drive loop length to each device short.
Do you have a design example for the gate driver?
Yes. Please see the gate driver application note GN001 section “Gate driver example”.
What is the substrate pad and how do I use it?
The Substrate pin is connected to the die substrate and is used as a thermal pad for cooling. It is electrically insulated from the drain and source connections on the bottom-side “P” packages. For these “P” package parts, always connect the substrate (thermal pad) to the source for best device performance. For the top-side packages “T” and the newer bottom-side packages “B”, the substrate pin is internally connected to the source pin.
What is most effective way to cool the device?
For GSxxxxP/B: bottom side cooling with a heat sink below the PCB and copper-filled vias underneath the device is the most effective cooling method. Additional cooling can be achieved by heat sinks on both the top and bottom sides of the devices. Please see application note GN005 for details. GSxxxxT devices are designed to be cooled by a heat sink on top of the device.
What is the recommended PCB layout for optimized thermal performance?
Please see thermal PCB layout application note GN005.
For the bottom-side cooled packages “P” and “B” can I attach a heat sink on the top side for cooling?
Cooling through the thermal pad is recommended as it has the best heat transfer. The top side of the package has higher thermal resistance but it also helps the overall thermal performance and can only be used in addition to the bottom side cooling if needed.
Please note that the top side of the device is covered by a layer of soldermask and is silkscreen printed. It has an uneven surface and is not designed to withstand high voltage or to provide safety insulation. If a heat sink is to be attached on the top, a layer of interface material with HV insulation must be added between the heat sink and the device to fill the gap and provide safety insulation.
Are the drain and source pads as thermally conductive as the thermal pad? Can thermal resistance be reduced by adding copper under drain and source pads?
Drain and source pads are not as thermally conductive as a thermal pad. Adding more copper under these two pads may reduce the packaging temperature at the edge but it does not affect the total junction to ambient thermal resistance.
Does the GaN enhancement mode HEMT have a body diode? How do the reverse conduction characteristics compare with a silicon MOSFET?
GaN Systems enhancement mode HEMTs do not have an intrinsic body diode and there is zero reverse recovery charge. The devices are naturally capable of reverse conduction and exhibit different characteristics depending on the gate voltage. At the system level, the reverse conduction capability can be an advantage compared to IGBTs because no anti-parallel diodes are required.
On-state (VGS = +6 V):
The reverse conduction characteristics of a GaN Systems enhancement mode HEMT in the on-state is similar to that of a silicon MOSFET, with the IV curve symmetrical about the origin and it exhibits a channel resistance RDS(ON) similar to forward conduction.
Off-state (VGS ≤ 0 V):
The reverse characteristics in the off-sate are different from silicon MOSFET as the GaN device has no body diode. In the reverse direction, the device starts to conduct when the gate voltage in respect to the drain (VGD) exceeds the gate threshold voltage and then the device exhibits a channel resistance. It can be modeled as a “body diode” with slightly higher VF and no reverse recovery charge.
If negative gate voltage is used in the off-state, the source-drain voltage must be higher than Vth+VGS (OFF) in order to turn the device on. Therefore, a negative gate voltage will add to the reverse voltage drop “VF” and hence increase the reverse conduction loss.
How much safety margin does the device have above the blocking voltage rating?
The blocking voltage rating BVDS is defined by the drain leakage current. The hard (unrecoverable) breakdown voltage is typically about 30% higher than the rated BVDS, or 2x the system DC voltage in most cases. As a general practice, the maximum drain voltage should be de-rated in a similar manner as IGBTs or silicon MOSFETs.
Does the maximum drain-to-source voltage rating change with junction temperature?
The maximum VDS voltage has a negative temperature coefficient.
What is the absolute maximum rating for Drain-to-Source voltage when negative voltage is applied to the Gate?
The absolute maximum drain-to-source rating is 650 V and doesn’t change with negative gate voltage.
What is the avalanche breakdown rating?
All E-HEMT GaN transistors do not avalanche and thus do not have an avalanche breakdown rating. GaN Systems’ transistors can withstand voltages higher than the rated voltage, typically 30% higher.
What is the temperature dependence of gate-source threshold voltage?
The GaN device exhibits a threshold voltage with a slightly positive temperature coefficient.
Can I parallel the GaN devices?
Yes. GaN enhancement mode HEMT devices have a positive temperature coefficient on-state resistance which helps to balance the current. However, special care should be taken in the driver circuit and PCB layout since the device switches at very fast speed. It is recommended to have a symmetric PCB layout and equal gate drive loop length on all parallel devices to ensure balanced dynamic current sharing.
What is the package material?
The package material is high temperature epoxy-based PCB material which is similar to FR4 but has a higher temperature rating, thus allowing our devices to be specified to 150°C.
How many reflow solder cycles can a device handle?
The device can handle at least 3 reflow cycles.
What is the recommended reflow temperature profile?
It is recommended to use the reflow profile in IPC/JEDEC J-STD-020 REV D.1 (March 2008)
The basic temperature profiles for Pb-free (Sn-Ag-Cu) assembly are:
- Preheat/Soak: 60-120 seconds. Tmin = 150°C, Tmax = 200°C.
- Reflow: Ramp up rate 3°C/sec, max. Peak temperature is 260°C and time within 5°C of peak temperature is 30 seconds.
- Cool down: Ramp down rate 6°C/sec max.
For SnPb assembly, preheat to 120-150°C and use peak temperature or 235°C for reflow.