Published in its entirety at EETimes.
By Maurizio Di Paolo Emilio, November, 12, 2020
It is a fact that GaN transistors have increased the performance of power systems while reducing the relative cost of components. But what about quality and reliability?
In an interview with EE Times, Jim Witham, CEO of GaN Systems, highlighted how the power transistor industry is familiar with the qualification guidelines in the Joint Electron Device Engineering Council (JEDEC) standards for silicon transistors as the foundation. But with GaN, device material is different, and hence, the failure modes and mechanisms are different.
Determining the guidelines for testing GaN under JEDEC and AEC-Q is part of the work that the GaN industry has studied, Witham pointed out. He added, “one result of this analysis is that the mission profiles that shape the life of electronic systems are changing. For example, internal combustion engine automobiles requiring 8,000 hours of service life have increased considerably for HEV/EV on-board chargers requiring >30,000 hours — almost a 4-fold increase”.
An Industry Approach
The GaN industry aims at demonstrating that GaN solutions have at least the same life expectancy as silicon MOSFETs, and ideally, a better life. The sector and the JEDEC JC-70 committees are working hard to define a series of tests, conditions, and pass/fail criteria for GaN and SiC devices to ensure system reliability and accelerate the market. Witham added the industry consortium is working hard to overcome differences — suppliers with different technologies with consequent bias and suppliers with different business interests — some have silicon and GaN, some only have GaN, others have silicon, SiC, and GaN.
“I believe one of the key elements is the product development cycle. What we do first is to design a product. Second is the qualification, where we stress the product with high voltage, high temperature, high relative humidity, and high frequency over time. Qualification tests are performed to ensure that semiconductor devices operate as designed both before and after stress. Next, we test the products to failure to show that all failure modes are understood. And then, the key is to ensure this information is included into the product development cycle. The whole process of understanding failure modes, redesigning, getting a longer life is very critical. Then the proof is in the numbers. And so, what we have proven is that GaN Systems transistors have lifetimes as good or better than the best silicon power transistors,” said Witham.
Witham pointed out that there are several challenges, however. Failure mechanisms can vary from supplier to supplier. Some suppliers may not have the right knowledge. For others who know their failure mechanisms, those companies can relate their mechanisms to testing and design to ensure long lifetime GaN transistors and overall system reliability.
In parallel with the efforts of JC-70, GaN Systems has undertaken a collaboration with several automotive & industrial customers to develop a strategy and qualification process to ensure reliability and robustness for GaN Systems’ devices. The key elements of the strategy can be summarized in device failures mode, transistor design, test design, and manufacturing process.
Witham also added that, “The results of the collaboration include the JEDEC standard and AEC-Q101 tests applied as a baseline and additional test methods implemented for the differences between Silicon and GaN in terms of material and failure modes. Failure measurements were identified using FMEA and test-to-failure methods, and all tests were performed for both extrinsic and intrinsic failure modes. We call these programs Enhanced JEDEC and AutoQual+ tests.”
After the proper design, extrinsic mechanisms are typically caused by an error in the manufacturing process – an assembly defect. These extrinsic defects need to be screened-out by tests by the manufacturer. Intrinsic mechanisms, on the other hand, are caused by the natural degradation of materials over the lifetime of the product in the application.
To demonstrate robustness and reliability, tests have been extended beyond JEDEC requirements. “An example of test performance extended to JEDEC is shown in Figure 1. The graphs show a stable performance at 5 times the test duration required for both the JEDEC test and the AEC-Q101 test specifications,” said Witham.