Webinar: Using Simulation to Maximize GaN Powered Design

Effective simulation tools are the key to efficient system design and debugging. GaN Systems provides both device-level and system-level simulation tools to help customers achieve design success. In this webinar, GaN Systems simulation tools will be introduced in detail, including model architectures, static and dynamic characterization for GaN devices, etc. Three examples of GaN-based systems will be presented with experimental results to verify the accuracy of different models.

In This Webinar You’ll Learn:

  • How to maximize system performance with GaN Systems simulation tools
  • How to use GaN Systems simulation tools
  • The key GaN features and characterization methods built into the simulation tools



Questions & Answers

The parasitic capacitance of GaN is already considered in the model. There is no need to add Cotr in parallel with the device.

The threshold voltage is implemented as fixed value in the model.

Application note GN002: Thermal Design for Packaged GaNPX® Devices discussed the top/bottom-cooled device thermal design considerations.

We use PCBs with 2-ounce copper thickness for most our high current design.

In the Python model: first, we define the system parameters. Then, the switching/conduction/deadtime loss calculation equations of GaN device are imported. Based on the system topology, operating principle, loss distribution and temperature iteration, we calculate the power stage loss and thermal results. For a complete system, we also add the loss equations for passive components such as inductor, output capacitor, etc.

The Spice models of GaN Systems devices can be downloaded from GaN System official website, on the individual product webpage.

Refer to our application note GN006 which includes the LTSpice simulation setup details.

Please see our application note GN009: PCB Layout Considerations with GaN E-HEMTs for details.

The error between the simulated results (Eon/Eoff) from GaN Systems LTSpice model and experimental results is less than 10%, which we think is good convergence.

This information is provided on a case-by-case basis, contact your local GaN Systems representative for further information.

The specific data for these measurements are applied to the correlation analysis between actual and simulation switching energy which is within an acceptable 10% margin.

The dynamic Rdson impact to overall system performance is negligible and is therefore not included in the model. Review our technical papers and webinar on the topic for more information.

Simulation is a good way to obtain the rise/fall time of GaN under certain conditions. With that information you can optimize the deadtime.

Consider layout changes, using negative gate-off voltage, increasing the gate resistance, and/or adding capacitance between gate and source to help improve mis-triggering. For more details refer to our app note and webinar on the topic: https://gansystems.com/wp-content/uploads/2019/01/GN009-PCB-Layout-Considerations-with-GaN-E-HEMTs_20190118.pdf, https://gansystems.com/webinar-simple-layout-steps-to-maximizing-gan-systems-design-performance-playback/

The I-V curves are obtained from static characterization test.

The decoupling capacitor is present to absorb the high frequency current and provide the energy during GaN switching.

The pin represents Source-Sense or Kelvin-Source, which is used for source connection on the gate-loop side.

Yes. We recommend using +6V as gate-on voltage of GaN.

With DPT, we measure switching-on loss at zero current. And we calculate zero current switching-off loss based on the data from the CV curve.

Download the Presentation from this Webinar

Moderator: Paul Wiener

VP Strategic Marketing at GaN Systems

Paul Wiener is GaN Systems’ Vice President of Strategic Marketing. Prior to joining GaN Systems, Paul led the power magnetics business unit at Eaton. Paul brings more than 25 years’ experience in operations, sales and marketing, and business development. His experience includes vice president of sales at Fultec Semiconductor Inc. and several management roles at Genoa, BroadLogic, and Raychem.

Skip to content